1. Field of the Invention
This invention relates to the method for fabricating semi-conductor devices, especially MOS devices, such as depletion mode MOS transistors.
2. Description of the Prior Art
A conventional manufacturing method for producing D-mode MOS transistor devices such as an E/D inverter is explained by reference to FIG. 1 to FIG. 8. As is shown in FIG. 1, a P-type silicon substrate 1 is provided. The silicon substrate 1 is oxidized to form a silicon oxide layer 2. Then by using conventional vapor phase deposition, silicon nitride layer 3 is deposited on the surface of silicon oxide layer 2. Next, on the surface of silicon nitride layer 3, a photoresist layer is provided. Then by using a conventional photo-engraving process, a desired resist pattern 4 is formed.
As is shown in FIG, 2, by using this photoresist pattern 4, a silicon nitride layer 3 is etched off to form silicon nitride layer patterns 3'. Thereafter, photoresist pattern 4 is removed and by using silicon layer pattern 3' as a mask, the whole substrate is heat-treated in a wet oxide atmosphere, thus forming field oxide layer S. In this process later mentioned nitride involved layer 5 as is shown in FIG. 3 is formed just underneath silicon oxide layer 2. Then as is shown in FIG. 4 silicon nitride pattern 3' is removed. Then, a selected part of the silicon oxide layer 2 and part of field oxide layer 5 is selectively etched off to form windows for impurity doping. Through these windows impurities, for example arsenic ions, are ion-implanted.
As is shown in FIG. 5, n layer 6 is formed to control the threshold value of n channel D-mode MOS transistor. After removing silicon oxide layer 2, gate oxide layer 7 is newly formed as is shown in FIG. 7. After that, forming of the gate electrode, diffusion, provision of the insulating layer, forming the contact hole through the insulating layer, metallization and forming of a protection layer are done and an E/D inverter using D-mode MOS semi-conductor devices is completed. In FIG. 8, the numerals 9a, 10a and 10b designate portions of an enhancement mode (E-mode) MOS transistor, wherein 10a is the source, 9a is the gate electrode, and 10b is the drain of this E-mode transistor. Also 9b, 10b and 10c designate portions of a D mode MOS transistor, wherein 9b is the gate electrode and 10b is the source of this D-mode transistor and 10c is the drain. In the channel, region 7 doped with N-type impurity exists. Then through insulating layer 11, electrodes 12a, 12b, 12 c and 12d to each region are formed. Electrodes 12a, 12b, 12c and 12d are, for example, made of aluminum. The whole surface is covered with a protection layer 13.
One of the disadvantages of this conventional method is the difficulty in providing a reliable silicon oxide layer 2 as a mask for doping impurities. This is mainly because of the fact that there is no ideal selective etching method for removing the silicon nitride layer 3' without attacking the silicon oxide layer 2. For example, even by using plasma etching, the etching ratio is 4:1. Besides that, when removing the silicon nitride layer 3', the etching rate or etching speed is different within wafers or among lots. Furthermore, the determination of the end of the etching period is very difficult, so normally the etching time is a little prolonged. Because of this, the silicon oxide layer 2 often becomes thinner than the desired value, whereupon this silicon oxide layer 2 may no longer function effectively as an impurity doping mask.
Another disadvantage is a phenomenon so-called white ribbon which is discussed in Journal of Electrochemical Society, Solid State Science and Technology, Vol. 123, No. 7, July 1976, pages 1117 to 1120.